View IDT71V802S133PFI_5288305.PDF datasheet online --- IC-ON-LINE

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december 2003 dsc-5311/07 1 ?2002 integrated device technology, inc. a 0 -a 18 address inputs input synchronous ce chip enable input synchronous cs 0 , cs 1 chip selects input synchronous oe output enable input asynchronous gw global write enable input synchronous bwe byte write enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 (1 ) individual byte write selects input synchronous clk clock input n/a adv burst address advance input synchronous adsc address status (cache controller) input synchronous adsp address status (processor) input synchronous lbo linear / interleaved burst order input dc zz sleep mode input asynchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data input / output i/o synchronous v dd , v ddq core power, i/o power supply n/a v ss ground supply n/a 5311 tbl 01 features u u u u u 256k x 36, 512k x 18 memory configurations u u u u u supports high system speed: C 166mhz 3.5ns clock access time C 150mhz 3.8ns clock access time C 133mhz 4.2ns clock access time u u u u u lbo lbo lbo lbo lbo input selects interleaved or linear burst mode u u u u u self-timed write cycle with global write control ( gw gw gw gw gw ), byte write enable ( bwe bwe bwe bwe bwe ), and byte writes ( bw bw bw bw bw x) u u u u u 3.3v core power supply u u u u u power down controlled by zz input u u u u u 2.5v i/o supply (v ddq ) u u u u u packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp), 119 ball grid array (bga) and 165 fine pitch ball grid array. pin description summary note: 1. bw 3 and bw 4 are not applicable for the idt71v67802. 256k x 36, 512k x 18 3.3v synchronous srams 2.5v i/o, burst counter pipelined outputs, single cycle deselect idt71v67602 idt71v67802 description the idt71v67602/7802 are high-speed srams organized as 256k x 36/512k x 18. the idt71v676/78 srams contain write, data, address and control registers. internal logic allows the sram to generate a self-timed write based upon a decision which can be left until the end of the write cycle. the burst mode feature offers the highest level of performance to the system designer, as the idt71v676 02 /78 02 can provide four cycles of data for a single address presented to the sram. an internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. the first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. if burst mode operation is selected ( adv =low), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. the order of these three addresses are defined by the internal burst counter and the lbo input pin. the idt71v67602/7802 srams utilize idts latest high-performance cmos process and are packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp) as well as a 119 ball grid array (bga) and 165 fine pitch ball grid array (fbga).
6.42 2 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect symbol pin function i/o active description a 0 -a 18 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk and adsc low or adsp low and ce low. adsc address status (cache controller) i low synchronous address status from cache controller. adsc is an active low input that is used to load the address registers with new addresses. adsp address status (processor) i low synchronous address status from processor. adsp is an active low input that is used to load the address registers with new addresses. adsp is gated by ce . adv burst address advance i low synchronous address advance. adv is an active low input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. when the input is high the burst counter is not incremented; that is, there is no address advance. bwe byte write enable i low synchronous byte write enable gates the byte write inputs bw 1 - bw 4 . if bwe is low at the rising edge of clk then bw x inputs are passed to the next stage in the circuit. if bwe is high then the byte write inputs are blocked and only gw can initiate a write cycle. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. bw 1 controls i/o 0-7 , i/o p1 , bw 2 controls i/o 8-15 , i/o p2 , etc. any active byte write causes all outputs to be disabled. ce chip enable i low synchronous chip enable. ce is used with cs 0 and cs 1 to enable the idt71v67602/7802. ce also gates adsp . clk clock i n/a this is the clock input. all timing references for the device are made with respect to this input. cs 0 chip select 0 i high synchrono us active high chip select. cs 0 is used with ce and cs 1 to enable the chip. cs 1 chip select 1 i low synchronous active low chip select. cs 1 is used with ce and cs 0 to enable the chip. gw global write enable i low synchronous global write enable. this input will write all four 9-bit data bytes when low on the rising edge of clk. gw supersedes individual byte write enables. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a synchro nous data input/output (i/o) pins. both the data input path and data output path are registered and triggered by the rising edge of clk. lbo linear burst order i low asynchronous burst order selection input. when lbo is high, the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input and must not change state while the device is operating. oe output enable i low asynchronous output enable. when oe is low the data output drivers are enabled on the i/o pins if the chip is also selected. when oe is high the i/o pins are in a high- impedance state. v dd power supply n/a n/a 3.3v core power supply. v ddq power supply n/a n/a 2.5v i/o supply. v ss ground n/a n/a ground. nc no connect n/a n/a nc pins are not electrically connected to the device. zz sleep mode i high asynchronous sleep mode input. zz high will gate the clk internally and power down the idt71v67602/7802 to its lowest power consumption level. data retention is guaranteed in sleep mode. 5311 tb l 02 pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk.
6.42 3 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect functional block diagram a 0C a 17/18 address register clr a1* a0* 18/19 2 18/19 a 2 Ca 18 256k x 36/ 512k x 18- bit memory array internal address a 0 ,a 1 bw 4 bw 3 bw 2 bw 1 byte 1 write register 36/18 36/18 adsp adv clk adsc cs 0 cs 1 byte 1 write driver byte 2 write driver byte 3 write driver byte 4 write driver byte 2 write register byte 3 write register byte 4 write register 9 9 9 9 gw ce bw e lb o i/o 0 Ci/o 31 i/o p1 Ci/o p4 oe data input register 36/18 output buffer output register d q dq enable register enable delay register oe burst sequence cen clk en clk en q1 q0 2 burst logic binary counter 5311 drw 01 zz powerdown ,
6.42 4 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect 100-pin tqfp capacitance (t a = +25c, f = 1.0mhz) recommended operating temperature and supply voltage absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supplies have ramped up. power supply sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating commercial unit v te r m (2 ) terminal voltage with re sp e ct to gnd -0.5 to +4.6 v v te r m (3,6) terminal voltage with re sp e ct to gnd -0.5 to v dd v v te r m (4,6) terminal voltage with re sp e ct to gnd -0.5 to v dd +0.5 v v te r m (5,6) terminal voltage with re sp e ct to gnd -0.5 to v ddq +0.5 v t a (7) commercial -0 to +70 o c ind ustrial -40 to +85 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 5311 tb l 03 grade temperature (1) v ss v dd v ddq commercial 0c to +70c 0v 3.3v5% 2.5v5% industrial -40c to +85c 0v 3.3v5% 2.5v5% 5311 tbl 04 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5311 tbl 07 symbol parameter min. typ. max. unit v dd core supply voltage 3.135 3.3 3.465 v v ddq i/o supply voltage 2.375 2.5 2.625 v v ss ground 0 0 0 v v ih input high voltage - inputs 1.7 ____ v dd +0.3 v v ih input high voltage - i/o 1.7 ____ v ddq +0.3 v v il input low voltage -0.3 (1) ____ 0.7 v 5311 tbl 06 recommended dc operating conditions note: 1. v il (min) = -1.0v for pulse width less than t cyc/2 , once per cycle. note: 1. t a is the "instant on" case temperature. 119 bga capacitance (t a = +25c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5311 tbl 07a 165 fbga capacitance (t a = +25c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5311 tbl 07b
6.42 5 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect pin configuration ? 256k x 36, 100-pin tqfp notes: 1. pin 14 can either be directly connected to v dd , or connected to an input voltage 3 v ih , or left unconnected. 2. pin 64 can be left unconnected and the device will always remain in active mode. 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 b w 4 b w 3 b w 2 b w 1 c s 1 v d d v s s c lk g w b w e o e a d s c a d s p a d v a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a 17 n c n c n c lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5311 drw 02 v dd /nc (1) i/o 15 i/o p3 nc i/o p4 a 15 a 16 i/o p1 nc i/o p2 zz (2) , top view
6.42 6 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect pin configuration ? 512k x 18, 100-pin tqfp 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 n c n c b w 2 b w 1 c s 1 v d d v s s c lk g w b w e o e a d s c a d s p a d v a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c lb o a 15 a 14 a 13 a 12 a 11 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5311 drw 03 v dd /nc (1) nc nc nc nc a 16 a 17 nc nc a 10 zz (2) , a 18 top view notes: 1. pin 14 can either be directly connected to v dd , or connected to an input voltage 3 v ih , or left unconnected. 2. pin 64 can be left unconnected and the device will always remain in active mode.
6.42 7 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect pin configuration ? 512k x 18, 119 bga pin configuration ? 256k x 36, 119 bga top view top view notes: 1. r5 can either be directly connected to v dd , or connected to an input voltage 3 v ih , or left unconnected. 2. t7 can be left unconnected and the device will always remain in active mode. 3. pin u6 will be internally pulled to v dd if not actively driven. to disable the tap controller without interfering with normal operation, trst should be tied low and tck, tdi, and tms should be pulled through a resistor to 3.3v. tdo should be left unconnected. 4. on future 18m device cs 0 will be removed, b2 will be be used for address expansion. 1234567 a v ddq a 6 a 4 adsp a 8 a 16 v ddq b nc cs 0 a 3 adsc a 9 a 17 nc c a 7 a 2 v dd a 12 a 15 nc d i/o 16 i/o p3 v ss nc v ss i/o p2 i/o 15 e i/o 17 i/o 18 v ss ce v ss i/o 13 i/o 14 f v ddq i/o 19 v ss oe v ss i/o 12 v ddq g i/o 20 i/o 21 bw 3 adv bw 2 i/o 11 i/o 10 h i/o 22 i/o 23 v ss gw v ss i/o 9 i/o 8 j v ddq v dd nc v dd nc v dd v ddq k i/o 24 i/o 26 v ss clk v ss i/o 6 i/o 7 l i/o 25 i/o 27 bw 4 nc bw 1 i/o 4 i/o 5 m v ddq i/o 28 v ss bwe v ss i/o 3 v ddq n i/o 29 i/o 30 v ss a 1 v ss i/o 2 i/o 1 p i/o 31 i/o p4 v ss a 0 v ss i/o 0 i/o p1 r nc a 5 lbo v dd a 13 t nc nc a 10 a 11 a 14 nc zz u v ddq dnu (3) dnu (3) dnu (3) dnu (3) dnu (3) v ddq 5311 drw 04 v dd /nc nc nc , (1) (2) (4) 1234567 a v ddq a 6 a 4 adsp a 8 a 16 v ddq b nc cs 0 (4) a 3 adsc a 9 a 18 nc c a 7 a 2 v dd a 13 a 17 nc d i/o 8 nc v ss nc v ss i/o p1 nc e nc i/o 9 v ss ce v ss nc i/o 7 f v ddq nc v ss oe v ss i/o 6 v ddq g nc i/o 10 bw 2 adv nc i/o 5 h i/o 11 nc v ss gw v ss i/o 4 nc j v ddq v dd nc v dd nc v dd v ddq k nc i/o 12 v ss clk v ss nc i/o 3 l i/o 13 nc nc bw 1 i/o 2 nc m v ddq i/o 14 v ss bwe v ss nc v ddq n i/o 15 nc v ss a 1 v ss i/o 1 nc p nc i/o p2 v ss a 0 v ss nc i/o 0 r nc a 5 lbo v dd a 12 t nc a 10 a 15 nc a 14 a 11 zz u v ddq dnu (3) dnu (3) dnu (3) dnu (3) dnu (3) v ddq 5311 drw 05 nc v dd /nc nc v ss v ss , (1) (2)
6.42 8 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect 1234567891011 anc (3) a 7 ce bw 3 bw 2 cs 1 bwe adsc adv a 8 nc bnc a 6 cs 0 bw 4 bw 1 clk gw oe adsp a 9 nc (3) ci/o p3 nc v ddq v ss v ss v ss v ss v ss v ddq nc i/o p2 di/o 17 i/o 16 v ddq v dd v ss v ss v ss v dd v ddq i/o 15 i/o 14 ei/o 19 i/o 18 v ddq v dd v ss v ss v ss v dd v ddq i/o 13 i/o 12 fi/o 21 i/o 20 v ddq v dd v ss v ss v ss v dd v ddq i/o 11 i/o 10 gi/o 23 i/o 22 v ddq v dd v ss v ss v ss v dd v ddq i/o 9 i/o 8 hv dd (1) nc nc v dd v ss v ss v ss v dd nc nc zz (2) ji/o 25 i/o 24 v ddq v dd v ss v ss v ss v dd v ddq i/o 7 i/o 6 ki/o 27 i/o 26 v ddq v dd v ss v ss v ss v dd v ddq i/o 5 i/o 4 li/o 29 i/o 28 v ddq v dd v ss v ss v ss v dd v ddq i/o 3 i/o 2 mi/o 31 i/o 30 v ddq v dd v ss v ss v ss v dd v ddq i/o 1 i/o 0 ni/o p4 nc v ddq v ss nc nc (3) nc v ss v ddq nc i/o p1 pnc nc (3) a 5 a 2 dnu (4) a 1 dnu (4) a 10 a 13 a 14 a 17 r lbo nc (3) a 4 a 3 dnu (4) a 0 dnu (4) a 11 a 12 a 15 a 16 5311 tbl 17a 1234567891011 anc (3) a 7 ce bw 2 nc cs 1 bwe adsc adv a 8 a 10 bnc a 6 cs 0 nc bw 1 clk gw oe adsp a 9 nc (3) cnc ncv ddq v ss v ss v ss v ss v ss v ddq nc i/o p1 dnc i/o 8 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 7 enc i/o 9 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 6 fnc i/o 10 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 5 gnc i/o 11 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 4 hv dd (1) nc nc v dd v ss v ss v ss v dd nc nc zz (2) ji/o 12 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 3 nc ki/o 13 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 2 nc li/o 14 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 1 nc mi/o 15 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 0 nc ni/o p2 nc v ddq v ss nc nc (3) nc v ss v ddq nc nc pnc nc (3) a 5 a 2 dnu (4) a 1 dnu (4) a 11 a 14 a 15 a 18 r lbo nc (3) a 4 a 3 dnu (4) a 0 dnu (4) a 12 a 13 a 16 a 17 5311 tbl 17b pin configuration ? 512k x 18, 165 fbga pin configuration ? 256k x 36, 165 fbga notes: 1. h1 can either be directly connected to v dd , or connected to an input voltage 3 v ih , or left unconnected. 2. h11 can be left unconnected and the device will always remain in active mode. 3. pin n6, b11, a1, r2 and p2 are reserved for 18m, 36m, 72m, and 144m and 288m respectively.
6.42 9 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect symbol parameter test conditions min. max. unit |i l i | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i lzz | zz and lbo input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v ddq , device deselected ___ 5a v ol output low voltage i ol = +6ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -6ma, v dd = min. 2.0 ___ v 5311 tbl 08 dc electrical characteristics over the operating temperature and supply voltage range (1) dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test load ac test conditions (v ddq = 2.5v) note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application and the zz pin will be internally pulled to v ss if not actively driven. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc while adsc = low; f=0 means no input lines are changing. 3. for i/os v hd = v ddq - 0.2v, v ld = 0.2v. for other inputs v hd = v dd - 0.2v, v ld = 0.2v. v ddq /2 50 w i/o z 0 =50 w 5311 drw 06 , 1 2 3 4 20 30 50 100 200 d t cd (typical, ns) capacitance (pf) 80 5 6 5311 drw 07 , symbol parameter test conditions 166mhz 150mhz 133mhz unit com'l only com'l ind com'l ind i dd operating power supply current device selected, outputs open, v dd = max., v ddq = max., v in > v ih or < v il , f = f max (2) 340 305 325 260 280 ma i sb1 cmos stand by po wer sup ply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = 0 (2,3) 50 50 70 50 70 ma i sb2 clock running powe r supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = f max (2,3) 160 155 175 150 170 ma i zz full sleep mode supply current zz > v hd, v dd = max. 50 50 70 50 70 ma 5311 tbl 09 input pulse levels input rise/fall times input timing reference levels output timing reference levels ac test load 0 to 2.5v 2ns v ddq /2 v ddq /2 see figure 1 5311 tb l 10
6.42 10 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect synchronous truth table (1,3) notes: 1. l = v il , h = v ih , x = dont care. 2. oe is an asynchronous input. 3. zz = low for this table. operation address used ce cs 0 cs 1 adsp adsc adv gw bwe bw x oe (2) clk i/o de se lected cycle, po wer down no ne h x x x l x x x x x - hi-z de se lected cycle, po wer down no ne l x h l x x x x x x - hi-z de se lected cycle, po wer down no ne l l x l x x x x x x - hi-z de se lected cycle, po wer down no ne l x h x l x x x x x - hi-z de se lected cycle, po wer down no ne l l x x l x x x x x - hi-z read cycle, begin burst external l h l l x x x x x l - d out read cycle, begin burst externallhl l x xxxxh-hi-z read cycle, begin burst external l h l h l x h h x l - d out read cycle, begin burst external l h l h l x h l h l - d out read cycle, begin burst external l h l h l x h l h h - hi-z write cycle, begin burst external l h l h l x h l l x - d in write cycle, begin burst external l h l h l x l x x x - d in read cycle, continue burst next x x x h h l h h x l - d out re ad cycle, continue burst next x x x h h l h h x h - hi-z read cycle, continue burst next x x x h h l h x h l - d out re ad cycle, continue burst next x x x h h l h x h h - hi-z read cycle, continue burst next h x x x h l h h x l - d out re ad cycle, continue burst next h x x x h l h h x h - hi-z read cycle, continue burst next h x x x h l h x h l - d out re ad cycle, continue burst next h x x x h l h x h h - hi-z write cycle, continue burst next x x x h h l h l l x - d in write cycle, continue burst next x x x h h l l x x x - d in write cycle, continue burst next h x x x h l h l l x - d in write cycle, continue burst next h x x x h l l x x x - d in read cycle, suspend burst current x x x h h h h h x l - d out read cycle, suspend burst current x x x h h h h h x h - hi-z read cycle, suspend burst current x x x h h h h x h l - d out read cycle, suspend burst current x x x h h h h x h h - hi-z read cycle, suspend burst current h x x x h h h h x l - d out read cycle, suspend burst current h x x x h h h h x h - hi-z read cycle, suspend burst current h x x x h h h x h l - d out read cycle, suspend burst currenthxx x h hhx hh -hi-z write cycle, suspend burst current x x x h h h h l l x - d in write cycle, suspend burst current x x x h h h l x x x - d in write cycle, suspend burst current h x x x h h h l l x - d in write cycle, suspend burst current h x x x h h l x x x - d in 5311 tbl 11
6.42 11 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect linear burst sequence table ( lbo =v ss ) synchronous write function truth table (1, 2) asynchronous truth table (1) interleaved burst sequence table ( lbo =v dd ) notes: 1. l = v il , h = v ih , x = dont care. 2. bw 3 and bw 4 are not applicable for the idt71v67802. 3. multiple bytes may be selected during the same cycle. notes: 1. l = v il , h = v ih , x = dont care. 2. synchronous function pins must be biased appropriately to satisfy operation requirements. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. operation gw bwe bw 1 bw 2 bw 3 bw 4 read hhxxxx read hlhhhh write all bytes l x x x x x write all bytes h l l l l l write byte 1 (3 ) hllhhh write byte 2 (3 ) hlhlhh write byte 3 (3 ) hlhhl h write byte 4 (3 ) hlhhhl 5311 tbl 12 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11000110 5311 tbl 15 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11100100 5311 tbl 14 operation (2 ) oe zz i/o status power read l l data out active read h l high-z active write x l high-z C data in active deselected x l high-z standby sleep mode x h high-z sleep 5311 tbl 13
6.42 12 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect ac electrical characteristics (v dd = 3.3v 5%, commercial and industrial temperature ranges) notes: 1. measured as high above v ih and low below v il . 2. transition is measured 200mv from steady-state. 3. device must be deselected when powered-up from sleep mode. 4. t cfg is the minimum time required to configure the device based on the lbo input. lbo is a static input and must not change during normal operation. 166mhz 150mhz 133mhz symbol parameter min. max. min. max. min. max. unit t cy c clock cycle time 6 ____ 6.7 ____ 7.5 ____ ns t ch (1 ) clock high pulse width 2.4 ____ 2.6 ____ 3 ____ ns t cl (1 ) clock low pulse width 2.4 ____ 2.6 ____ 3 ____ ns output parameters t cd clock high to valid data ____ 3.5 ____ 3.8 ____ 4.2 ns t cd c clo ck high to data change 1.5 ____ 1.5 ____ 1.5 ____ ns t cl z (2 ) clock high to output active 0 ____ 0 ____ 0 ____ ns t chz (2 ) cl ock high to data high-z 1.5 3.5 1.5 3.8 1.5 4.2 ns t oe output enable access time ____ 3.5 ____ 3.8 ____ 4.2 ns t ol z (2 ) output enab le low to output active 0 ____ 0 ____ 0 ____ ns t ohz (2 ) output enab le high to output high-z ____ 3.5 ____ 3.8 ____ 4.2 ns set up times t sa address setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t ss address status setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sd data in setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sw write setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sav address advance setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sc chip enable/select setup time 1.5 ____ 1.5 ____ 1.5 ____ ns hold times t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hs address status hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw write hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hav address advance hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns sleep mode and configuration parameters t zzp w zz pulse width 100 ____ 100 ____ 100 ____ ns t zzr (3 ) zz re co ve ry time 100 ____ 100 ____ 100 ____ ns t cf g (4 ) configuration set-up time 24 ____ 27 ____ 30 ____ ns 5311 tbl 16
6.42 13 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect notes: 1. o1 (ax) represents the first output from the external address ax. o1 (ay) represents the first output from the external addr ess ay; o2 (ay) represents the next output data in the burst sequence of the base address ay, etc. where a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. zz input is low and lbo is don't care for this cycle. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of pipelined read cycle (1,2) t c h z t s a t s c t h s g w ,bw e, bw x t s w t c l t s a v t h w t h a v c lk a d s c (1) a d d r e s s t c y c t c h t h a t h c t o e t o h z o e t c d t o lz o 1(a x) d a ta o u t t c d c o 1(a y) o 3(a y) o 2(a y) o 2(a y) t c lz a d v c e ,c s 1 (n ote 3) p ipelined r ead b urst p ipelined r ead o utput d isabled a x a y t s s o 1(a y) (b urst w raps around to its initial state) o 4(a y) 5311 drw 08 a d s p a d v h ig h suspends burst ,
6.42 14 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect notes: 1. device is selected through entire cycle; ce and cs 1 are low, cs 0 is high. 2. zz input is low and lbo is don't care for this cycle. 3. o1 (ax) represents the first output from the external address ax. i1 (ay) represents the first input from the external addre ss ay; o1 (az) represents the first output from the external address az; o2 (az) represents the next output data in the burst sequence of the base address az, etc. where a0 and a1 are advancing fo r the four word burst in the sequence defined by the state of the lbo input. timing waveform of combined pipelined read and write cycles (1,2,3) c lk a d s p a d d r e s s g w a d v o e d ata o u t t c y c t c h t c l t h a t s w t h w t c lz a x a y a z t h s i1(a y) t s d t h d t o lz t c d t c d c d a ta in (2) t o e o 1(a z) o 1(a z) s ingle r ead p ipelined b urst r ead p ipelined w rite o 1(a x) t o h z t s s t s a o 3(a z) o 2(a z) 5311 drw 09 t c d ,
6.42 15 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect notes: 1. zz input is low, bwe is high and lbo is don't care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input fr om the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc. where a 0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2 (ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of write cycle no. 1 ? gw controlled (1,2,3) a d d r e s s c lk a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y a z a d v d a ta o u t o e t h c t s d i1(a x) i1(a z) i2(a y) th d t o h z d a ta in t h a v o 3(a w ) o 4(a w ) c e ,c s 1 t h w g w t s w (n ote 3) i2(a z) b urst w rite b urst r ead b urst w rite s ingle w rite i3(a z) i4(a y) i3(a y) i2(a y) t s a v ( a d v h ig h suspends burst) i1(a y) g w is ignored w hen a d s p initiates a cycle and is sam p led on the n ext clock rising e dg e t s c 5311 drw 10 ,
6.42 16 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect timing waveform of write cycle no. 2 ? byte controlled (1,2,3) a d d r e s s c lk a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y t h w b w x a d v d ata o u t o e t h c t s d s ingle w rite b urst w rite i1(a x) i2(a y) i2(a y) ( a d v suspends burst) i2(a z) th d b urst r ead e xtended b urst w rite t o h z d a ta in t s a v t s w o 4(a w ) c e ,c s 1 t h w b w e t s w (n ote 3) i1(a z) a z i4(a y) i1(a y) i4(a y) i3(a y) t s c b w e is ignored w hen a d s p initiates a cycle and is sam pled on next clock rising edge b w x is ignored w hen a d s p initiates a cycle and is sam pled on next clock rising edge i3(a z) o 3(a w ) 5311 drw 11 , notes: 1. zz input is low, gw is high and lbo is don't care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input fr om the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc. where a 0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2 (ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high.
6.42 17 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect timing waveform of sleep (zz) and power-down modes (1,2,3) t c y c t s s t c l t c h t h a t s a t s c t h c t o e t o lz t h s c lk a d s p a d s c a d d r e s s g w c e ,c s 1 a d v d a t a o u t o e z z s ingle r ead s nooze m ode tzz p w 5311 drw 12 o 1(a x) a x (n ote 4) tz z r a z , notes: 1. device must power up in deselected mode 2. lbo is don't care for this cycle. 3. it is not necessary to retain the state of the input registers throughout the power-down cycle. 4. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs1 are low on this waveform, cs 0 is high.
6.42 18 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect clk adsp gw,bwe,bwx ce, cs 1 cs 0 address adsc data out oe av aw ax ay az (av) (aw) (ax) (ay) 5311 drw 14 , non-burst read cycle timing waveform notes: 1. zz input is low, adv is high and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. for read cycles, adsp and adsc function identically and are therefore interchangable. notes: 1. zz input is low, adv and oe are high, and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. although only gw writes are shown, the functionality of bwe and bw x together is the same as gw . 4. for write cycles, adsp and adsc have different limitations. non-burst write cycle timing waveform clk adsp gw ce, cs 1 cs 0 address adsc data in av aw ax az ay (av) (aw) (ax) (az) (ay) 5311 drw 15 ,
6.42 19 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect 100-pin thin plastic quad flatpack (tqfp) package diagram outline
6.42 20 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect 119 ball grid array (bga) package diagram outline
6.42 21 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect 165 fine pitch ball grid array (fbga) package diagram outline
6.42 22 idt71v67602, idt71v67802, 256k x 36, 512k x 18, 3.3v synchronous commercial and industrial temperature ranges srams with 2.5v i/o, pipelined outputs, single cycle deselect ordering information 100-pin plastic thin quad flatpack (tqfp) 119 ball grid array (bga) 165 fine pitch ball grid array s power x speed xx package pf bg bq idt xxx 166* 150 133 frequency in megahertz 5311 drw 13 device type 71v67602 71v67802 256k x 36 pipelined burst synchronous sram 512k x 18 pipelined burst synchronous sram , blank i xx process/temp range commercial (0c to +70c) industrial (-40c to +85c) * industrial temperature not available on 166mhz devices

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